Apply For Staff /Senior Design Engineer IP/Sub-System

• Tenstorrent
• Office Location
• Full Time

Experience: 5 - 5 years required

Pay:

Salary Information not included

Type: Full Time

Location: All India

Skills: Verilog, System Verilog, ARM, AXI, AHB, APB, Power analysis, ASIC development, RISCV, CHI, Functional safety implementation, IP Quality checks, DV tools, Physical Design implementation, Static Timing report analysis, Logical Equivalence Checking, DesignforPower, DesignforDebug, DesignforTest