Apply For STA Design Engineers

• Mirafra Technologies
• Office Location
• Full Time

Experience: 1 - 1 years required

Pay:

Salary Information not included

Type: Full Time

Location: Noida

Skills: timing closure, static timing analysis, tcl scripting, FPGA Design, RTL design, Verilog, VHDL, Quartus, tcl scripting, PD experience, Placement, Routing, Timing Constraints, ASIC, FPGA software tool chain, Vivado, Digital design fundamentals, Wireless Domain, Wired domain