Mirafra Technologies
Employees - 100+, Positions - 8+, Salary - 0 - 0 , Industry Type - IT - Software
Mirafra Technologies Overview
Mirafra Technologies Active Jobs
FPGA Design Prototyping Lead
Mirafra Technologies
Office Location
Full Time
- Verilog
- System Verilog
- VHDL
- FPGAbased prototype platforms
- Xilinx AMD Vivado toolchain
- SynopsysMentor FPGA synthesis flow
- Virtex7
- Virtex Ultrascale
- Virtex Ultrascale Architectures
- CC
- ARM core architectures
Salary Information not included
RTL Architect
- Mirafra Technologies
- Office Location
- Full Time
- Microarchitecture
- Verification
- synthesis
- timing closure
- CPU
- SoC development
- fullchip design
- design convergence cycle
- IP dependencies
- Frontend design
- highspeed serial IO protocols
- clock rate compensation FIFO
- Gearbox Design
- Power Gating
- low power modes
- bus fabrics
- coherencenoncoherent NOC domains
Salary Information not included
AOSP, USB, CAMERA Developer
- Mirafra Technologies
- Office Location
- Full Time
- Debugging
- written communication
- Verbal communication
- collaboration
- AOSP
- USB driver development
- camera driver integration
- Problemsolving
Salary Information not included
Accelerated Verification
- Mirafra Technologies
- Office Location
- Full Time
- SIMXL
- Emulation Platform
- CC Coding
- SoC testbench
- bootup flows
- Zebu build creation
- debug capabilities
Salary Information not included
FPGA Lead
- Mirafra Technologies
- Office Location
- Full Time
- System design
- Verilog
- System Verilog
- VHDL
- synthesis
- timing closure
- silicon validation
- Failure analysis
- Debugging
- Embedded software
- github
- SVN
- Perl
- digital fundamentals
- FPGA devices
- FPGA EDA tools
- C code
- Embedded processors
- STA constraint definition
- ARM CortexM3
- RISCV
- AMBA protocols
- Bare metal application development
- Board level debug
- oscilloscopes
- Digital analyzers
- Protocol exercisers
- logic analyzers
- Tcl
Salary Information not included
STA Design Engineers
- Mirafra Technologies
- Office Location
- Full Time
- timing closure
- static timing analysis
- tcl scripting
- FPGA Design
- RTL design
- Verilog
- VHDL
- Quartus
- tcl scripting
- PD experience
- Placement
- Routing
- Timing Constraints
- ASIC
- FPGA software tool chain
- Vivado
- Digital design fundamentals
- Wireless Domain
- Wired domain
Salary Information not included
Design Verification Lead
- Mirafra Technologies
- Office Location
- Full Time
- SOC
- IP Verification
- System Verilog
- OVM
- UVM
- VMM
- PCIe
- DDR
- Ethernet
- UFS
- CHI
- ProcessorARM Based SoC Verification
Salary Information not included
SOC Verification Engineer( 5 to 12Yrs)
- Mirafra Technologies
- Office Location
- Full Time
- Verilog
- SystemVerilog
- RTL Coding
- CC
- UVM methodology
- JTAG protocol