Apply For Sr Principal RTL Design Engineer

• Cadence Design Systems
• Office Location
• Full Time

Experience: 12 - 12 years required

Pay:

Salary Information not included

Type: Full Time

Location: Karnataka

Skills: ASIC design, Verilog Coding, RTL design, PCIe, USB, Ethernet, SATA, Lint, SDC, CDC, LEC, UCIe, MIPIDPHY, HDMIDisplay, RTL checks, synthesis flow, Timing Constraints, Verilog testbench, Simulations