Sr Principal RTL Design Engineer Cadence Design Systems
Cadence Design Systems
Office Location
Full Time
Experience: 12 - 12 years required
Pay:
Salary Information not included
Type: Full Time
Location: Karnataka
Skills: ASIC design, Verilog Coding, RTL design, PCIe, USB, Ethernet, SATA, Lint, SDC, CDC, LEC, UCIe, MIPIDPHY, HDMIDisplay, RTL checks, synthesis flow, Timing Constraints, Verilog testbench, Simulations
About Cadence Design Systems
Job Description
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. 12+ years of experience in ASIC design Proficient in Verilog coding, RTL design and complex control path and data path designs Knowledge of any of the interface Protocols like UCIe, PCIe, USB, MIPI(DPHY), HDMI/Display, Ethernet, SATA Knowledge of RTL checks ex- LINT, SDC, CDC Familiar with synthesis flow, LEC and timing constraints Experience in writing Verilog testbench and running simulations. Were doing work that matters. Help us solve what others cant.,