Apply For Senior RTL Design Engineers

• ACL Digital
• Office Location
• Full Time

Experience: 3 - 3 years required

Pay:

Salary Information not included

Type: Full Time

Location: Hyderabad

Skills: RTL, Verilog, System Verilog, Logic synthesis, timing closure, SoC architecture, IP Development, AXI bus protocols, Hardware Debug, Xilinx FPGAs, Vivado tool flows, Micro architecture development