Senior RTL Design Engineers ACL Digital
ACL Digital
Office Location
Full Time
Experience: 3 - 3 years required
Pay:
Salary Information not included
Type: Full Time
Location: Hyderabad
Skills: RTL, Verilog, System Verilog, Logic synthesis, timing closure, SoC architecture, IP Development, AXI bus protocols, Hardware Debug, Xilinx FPGAs, Vivado tool flows, Micro architecture development
About ACL Digital
Job Description
As a Senior RTL Design Engineer with 3-5 years of experience, you will be based in Hyderabad. You will be required to demonstrate strong RTL (Verilog/System Verilog) skills with a focus on IP development. Your responsibilities will include verifying designs by creating simple testbenches, as well as possessing a solid foundation in logic synthesis and timing closure concepts. Additionally, you should have a good understanding of SoC architecture, AXI bus protocols, and hardware debug processes. Experience with Xilinx FPGAs, Vivado tool flows, and micro-architecture development will be considered a plus. If you meet the specified requirements and are interested in this opportunity, please submit your updated resume to janagaradha.n@acldigital.com.,