Apply For Senior Design Verification Lead /Manager

• BITSILICA
• Office Location
• Full Time

Experience: 8 - 8 years required

Pay:

Salary Information not included

Type: Full Time

Location: Hyderabad

Skills: Verilog, SystemVerilog, UVM, SoC design, ASIC design, ASIC Verification, USB, PCIe, UFS, SATA, Ethernet, AMBA, AXI, APB, AHB, ASIC, Stateoftheart verification methodologies, SystemVerilog Assertions, SVA, Scoreboard architecture