Senior Design Verification Lead /Manager BITSILICA
BITSILICA
Office Location
Full Time
Experience: 8 - 8 years required
Pay:
Salary Information not included
Type: Full Time
Location: Hyderabad
Skills: Verilog, SystemVerilog, UVM, SoC design, ASIC design, ASIC Verification, USB, PCIe, UFS, SATA, Ethernet, AMBA, AXI, APB, AHB, ASIC, Stateoftheart verification methodologies, SystemVerilog Assertions, SVA, Scoreboard architecture
About BITSILICA
Job Description
Summary: Over 8 years of experience in digital IP verification with a strong understanding of ASIC/SoC design and state-of-the-art verification methodologies. Proficient in Verilog, SystemVerilog, and UVM, with solid expertise in developing and maintaining UVM-based verification frameworks, testbenches, and processes. Strong grasp of UVM concepts, including SystemVerilog Assertions (SVA) and scoreboard architecture. Familiar with industry-standard high-speed protocols such as USB, PCIe, UFS, SATA, and Ethernet. Well-versed with standard interconnects like AMBA (AXI, APB, AHB).,