Apply For RTL ASIC Front End Design Engineer/ Lead

• Tessolve
• Office Location
• Full Time

Experience: 5 - 5 years required

Pay:

Salary Information not included

Type: Full Time

Location: Karnataka

Skills: Microarchitecture, Verilog Coding, I2C, SPI, UART, APB, AHB, AXI, Lint, CDC, RTL Coding, Team Leadership, RTL ASIC front end design, MAS development, Development of module, Medium complexity protocol, AMBA bus protocols, Quality check flows, MicroArchitechture, IP design, Subsystem design, soc integration