RTL ASIC Front End Design Engineer/ Lead Tessolve
Tessolve
Office Location
Full Time
Experience: 5 - 5 years required
Pay:
Salary Information not included
Type: Full Time
Location: Karnataka
Skills: Microarchitecture, Verilog Coding, I2C, SPI, UART, APB, AHB, AXI, Lint, CDC, RTL Coding, Team Leadership, RTL ASIC front end design, MAS development, Development of module, Medium complexity protocol, AMBA bus protocols, Quality check flows, MicroArchitechture, IP design, Subsystem design, soc integration
About Tessolve
Job Description
You will be responsible for RTL ASIC front end design with Microarchitecture and Verilog coding. Your tasks will include MAS development, RTL coding, development of modules, and feature additions. You should have experience in working with medium complexity protocols and be well-versed in slow-speed protocols like I2C, SPI, and UART. Familiarity with AMBA bus protocols (APB, AHB, AXI) is required. Additionally, you should have experience in Quality check flows, including lint and CDC. For candidates with 8+ years of experience, you are expected to be very strong in RTL coding. Your role will involve microarchitecture development, owning and delivering a subsystem or top level in a SoC project, expertise in IP design, subsystem design, SoC integration, and successful leadership of a team to deliver projects on time. If you are interested in this position, please share your updated CV with gayatri.kushe@tessolve.com or connect on 6361542656.,