Apply For PE And LB Timing

• ACL Digital
• Office Location
• Full Time

Experience: 5 - 5 years required

Pay:

Salary Information not included

Type: Full Time

Location: Karnataka

Skills: Embedded C, C, Python, LIB timing file generation, Verilog Modelling, Analog design characterization, EMIR simulation, Embedded product knowledge like UFS, eMMC, Automation background, Experience on debugging using T32