Apply For Field-Programmable Gate Arrays Engineer

• ACL Digital
• Office Location
• Full Time

Experience: 5 - 5 years required

Pay:

Salary Information not included

Type: Full Time

Location: Hyderabad

Skills: RTL design, RTL development, FPGA, VHDL, Verilog, Ethernet, PCIe, SPI, I2C, USB, GPIO, DDR, SDRAM, dma, Scripting, Perl, Python, Debugging, Xilinx, Memory Architectures, HW testing, Tcl