Field-Programmable Gate Arrays Engineer ACL Digital
ACL Digital
Office Location
Full Time
Experience: 5 - 5 years required
Pay:
Salary Information not included
Type: Full Time
Location: Hyderabad
Skills: RTL design, RTL development, FPGA, VHDL, Verilog, Ethernet, PCIe, SPI, I2C, USB, GPIO, DDR, SDRAM, dma, Scripting, Perl, Python, Debugging, Xilinx, Memory Architectures, HW testing, Tcl
About ACL Digital
Job Description
As a Silicon Design Engineer with over 5 years of experience in RTL design and development, you will be responsible for creating RTL designs and developing various documents such as requirements specification, design, user guides, etc. Your expertise in FPGA VHDL and/or Verilog design using Xilinx technology and tools will be crucial in this role. Additionally, your experience with Ethernet, PCIe, SPI, I2C, USB, GPIO, Memory architectures, DDR, SDRAM, DMA technologies, and hardware testing will be valuable assets. You should be adept at HW testing, including working with test equipment such as logic and traffic analyzers, test generators, etc. Strong debugging skills at both device and board levels will be essential. Proficiency in scripting languages like Perl, Python, or TCL will be beneficial. Your excellent interpersonal, written, and verbal communication skills will enable you to collaborate effectively with cross-functional teams. Moreover, your problem-solving and analytical skills will be put to good use in this dynamic role. If you are interested in this opportunity, please submit your updated resume to janagaradha.n@acldigital.com. Your contributions as a Silicon Design Engineer will play a vital role in the successful development of cutting-edge technology solutions.,