Apply For ASIC/RTL Design Engineer - SoC

• CAPRUS IT PRIVATE LIMITED
• Office Location
• Full Time

Experience: 5 - 5 years required

Pay:

Salary Information not included

Type: Full Time

Location: Hyderabad

Skills: Logic design, RTL Coding, SoC design, Integration, Verilog, SystemVerilog, Lint, CDC, synthesis, Formal Verification, AXI, AHB, APB, Scripting, Automation, UVM, PCIe, USB, DDR, Multi Clock designs, Asynchronous interface, ASIC development, ECO fixes, AMBA protocols, SoC clocking, Reset architecture, Verification cycle, Functional Coverage matrix, Comprehensive Test plan, Regression management, DUT integration, Verification IP development, System Verilog Assertions, release process, Simulations, regressions, Eth