ASIC/RTL Design Engineer - SoC CAPRUS IT PRIVATE LIMITED
CAPRUS IT PRIVATE LIMITED
Office Location
Full Time
Experience: 5 - 5 years required
Pay:
Salary Information not included
Type: Full Time
Location: Hyderabad
Skills: Logic design, RTL Coding, SoC design, Integration, Verilog, SystemVerilog, Lint, CDC, synthesis, Formal Verification, AXI, AHB, APB, Scripting, Automation, UVM, PCIe, USB, DDR, Multi Clock designs, Asynchronous interface, ASIC development, ECO fixes, AMBA protocols, SoC clocking, Reset architecture, Verification cycle, Functional Coverage matrix, Comprehensive Test plan, Regression management, DUT integration, Verification IP development, System Verilog Assertions, release process, Simulations, regressions, Eth
About CAPRUS IT PRIVATE LIMITED
Job Description
Required Skills Experience in Logic design / RTL coding is a must. Experience is SoC design and integration for complex SoCs is a must. Experience in Verilog/System-Verilog is a must. Experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint and CDC. Experience in Synthesis / Understanding of timing concepts is a plus. Experience in ECO fixes and formal verification. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset architecture. Excellent oral and written communications skills. Proactive, creative, curious, motivated to learn and contribute with good collaboration skills. Roles & Responsibilities Understand the standards/specifications Architecture development and documenting implementation level details Hands on work for every aspect of verification cycle Responsible for the compliance with the latest Methodologies. Developing Verification IPs Define Functional Coverage matrix and Comprehensive Test plan Regression management and functional coverage closure DUT integration and verification for IP delivery sign-off Leading small team Person Skills : Hands-on experience of complete verification cycle with strong verification concepts - Strong knowledge of Verilog, SystemVerilog and UVM- Experience in UVM based Verification IP development Experience in AMBA AXI/AHB/APB System buses Hands on work experience on any of PCIe/Eth/USB/DDR etc. Hands on experience with System Verilog Assertions Scripting for automation, release process, simulations, regressions Good command over written and oral Skills : Lead the Verification IP development with 2 or more junior engineers Exposure to full verification cycle Desired Skills And Experience DV Engineer, Design Verification, Verification Engineer (ref:hirist.tech),