Apply For ASIC RTL Designers Lint/CDC

• Sequentia Technologies Pvt Ltd
• Office Location
• Full Time

Experience: 2 - 2 years required

Pay:

Salary Information not included

Type: Full Time

Location: Karnataka

Skills: System design, Verilog, SV, VHDL, CDC, Logic design, ASIC Synthesis, STA, timing closure, SOC, AXI, AHB, PCIe, DDR, USB, UART, SPI, I2C, synthesis, timing analysis, micro architecture design, Spyglass Lint, soc integration, Processor based system design, APB System bus, peripherals Ethernet, Tcl, Python Scripting