ASIC RTL Designers Lint/CDC Sequentia Technologies Pvt Ltd
Sequentia Technologies Pvt Ltd
Office Location
Full Time
Experience: 2 - 2 years required
Pay:
Salary Information not included
Type: Full Time
Location: Karnataka
Skills: System design, Verilog, SV, VHDL, CDC, Logic design, ASIC Synthesis, STA, timing closure, SOC, AXI, AHB, PCIe, DDR, USB, UART, SPI, I2C, synthesis, timing analysis, micro architecture design, Spyglass Lint, soc integration, Processor based system design, APB System bus, peripherals Ethernet, Tcl, Python Scripting
About Sequentia Technologies Pvt Ltd
Job Description
The position requires 2-6 years of experience with micro architecture design and system design using Verilog, SV, or VHDL. You should also have experience in Spyglass Lint, CDC, SoC Integration, logic design with Verilog and SV, ASIC Synthesis, STA, timing closure, and working with any Processor based system. Familiarity with design using SoC, AXI/AHB/APB System bus, and peripherals such as Ethernet, PCIe, DDR, USB, UART, SPI, and I2C is essential. You will be responsible for synthesis, timing analysis using various industry standard tools, and should have proficiency in TCL and Python scripting. The ideal candidate for this role should have a notice period of immediate availability to 1 month. The position is based in BLR/Hyd locations.,