Apply For ASIC RTL Design Lead

• Modernize Chip Solutions (MCS)
• Office Location
• Full Time

Experience: 10 - 10 years required

Pay:

Salary Information not included

Type: Full Time

Location: Hyderabad

Skills: RTL design, Verilog, SOC, PCIe, Ethernet, Lint, CDC, synthesis, tcl scripting, PERL scripting, timing analysis, Subsystem integration, USB Integration, Front end flow environment bringup, Flows, Formality, VCLP, CDC constraint development, Signoff