Apply For ASIC Digital Verification, Sr Staff Engineer

• Synopsys
• Office Location
• Full Time

Experience: 2 - 2 years required

Pay:

Salary Information not included

Type: Full Time

Location: Karnataka

Skills: Verilog HDL, ASIC design, synthesis, Simulation, Verification, Serdes, MIPI UFSUniPro protocols, Parallel interfaces, Synopsys tool suites, English Communication Skills