Synopsys
Employees - 100+, Positions - 28+, Salary - 0 - 3 Lacs, Industry Type - IT - Software
Synopsys Overview
Synopsys Active Jobs
Sr Staff Simulation R&D Software Engineer
Synopsys
Office Location
Full Time
- Data structures
- algorithms
- object oriented programming
- Compiler design
- C Coding
- Agile Scrum frameworks
- simulation concepts
Salary Information not included
ASIC Digital Verification, Sr Staff Engineer
- Synopsys
- Office Location
- Full Time
- Verilog HDL
- ASIC design
- synthesis
- Simulation
- Verification
- Serdes
- MIPI UFSUniPro protocols
- Parallel interfaces
- Synopsys tool suites
- English Communication Skills
Salary Information not included
Low Power Architect
- Synopsys
- Office Location
- Full Time
- optimization
- Digital Design
- physical design
- UPF
- ASIC design methodology
- low power analysis
- Timing Signoff
- Advanced Nodes
- Timing Constraints
- SAIFbased analysis
- Software Skills
- scripting skills
- CAD automation methods
Salary Information not included
Analog Design Automation, Sr Engineer
- Synopsys
- Office Location
- Full Time
- Automation
- Data Engineering
- Python
- Perl
- Data extraction
- Data Transformation
- Data Analysis
- SEMICONDUCTOR TECHNOLOGY
- analogmixedsignal CAD tools
- SQL databases
Salary Information not included
Financial Planning & Analysis, Staff
- Synopsys
- Office Location
- Full Time
- Financial planning
- Financial Analysis
- SAP BPC
- SAP BW
- Excel
- Power Bi
- Tableau
- Python
- MIS
- Analytics
Salary Information not included
Test & Validation Engineer, Staff
- Synopsys
- Office Location
- Full Time
- static timing analysis
- Synopsys PrimeTime
- Extraction
- Debugging
- Perl
- Python
- ECO Flows
- SDC constraints
- OCV concepts
- Derates
- PBA timing
- Hierarchical STA flows
- Physical design closure
- Tcl
Salary Information not included
R&D Project and Technology Enabler
- Synopsys
- Office Location
- Full Time
- Programming Languages
- agile development
- Artifactory
- Databases
- Web Servers
- Linux platform
- CICD tools
- automation scripts
- Frontend Development
- backend development
- frameworks
- Build systems
- Application analyticsmonitoring
- Package managers
- UIUX design principles
- Full Stack Developer
- frontend languages
- libraries
- backend languages
- JavaScript frameworks
Salary Information not included
R&D Engineering, Director
- Synopsys
- Office Location
- Full Time
- C
- Linux
- Benchmarking
- Computer Science
- computer engineering
- Electrical engineering
- Software Development
- Interpersonal Skills
- Communication
- collaboration
- Innovation
- RTL simulation
- EmulationPrototyping
- Runtime Performance Improvements
- technical problem solving
Salary Information not included
Principal Solutions Engineer-SLM-10746
- Synopsys
- Office Location
- Full Time
- Project Management
- Communication skills
- leadership skills
- Agile project management
- CAD
- Digital Design
- Electrical engineering
- Computer Science
- Technical Project Management
- VLSI Engineering Tools
- Synopsys Tool set
Salary Information not included
R&D Engineering, Manager - PD - PPA Methodologies
- Synopsys
- Office Location
- Full Time
- Team Leadership
- Communication skills
- Interpersonal Skills
- Strategic Thinking
- highperformance coresIPs implementation
- methodologies development
- Synopsys implementation tools
- PPA methodologies
- technology nodes understanding
- Resultsdriven mindset
Salary Information not included
SerDes PHY Digital Design Engineer
- Synopsys
- Office Location
- Full Time
- Analog Design
- CMOS processes
- Deep submicron process technologies
- ASIC design flow
- JEDEC requirements
- DDRHBM Memory Interface
- ESD concepts
Salary Information not included
ASIC Digital Verification Engineer
- Synopsys
- Office Location
- Full Time
- UVM
- SystemVerilog
- C
- Perl
- Python
- Tcl
- assertion verification
- Coverage analysis
- protocoloriented performance analysis
Salary Information not included
Senior Research and Development Engineer-Foundry-10153
- Synopsys
- Office Location
- Full Time
- Verilog
- System Verilog
- UVM
- CC
- Python Scripting
Salary Information not included
Serdes/PCIe IP Application Engineer (post-sale)
- Synopsys
- Office Location
- Full Time
- RTL Coding
- Verilog
- Simulation
- synthesis
- scripting languages
- Perl
- Python
- Package Design
- PCB Design
- static timing check
- equivalence check
- PCI Express
- CXL
- Ethernet Protocols
- Tcl
- Excel VBA
- Silicon debug
- FPGAhardware troubleshooting
- SIPI Knowledge
Salary Information not included
Applications Engineering, Sr Engineer
- Synopsys
- Office Location
- Full Time
- RD
- Applications Engineer
- Synopsys StarRC
- Quickcap
- foundry RC technology
Salary Information not included
Principle Emulation Development Engineer
- Synopsys
- Office Location
- Full Time
- OOPS
- HDL
- System Verilog
- Verilog
- Perl
- HDMI
- MIPI
- AMBA
- UART
- UVM
- Functional verification
- CC
- Tcl
- ENET
Salary Information not included
Test & Validation Engineer
- Synopsys
- Office Location
- Full Time
- static timing analysis
- Synopsys PrimeTime
- Extraction
- Debugging
- Perl
- Python
- ECO Flows
- SDC constraints
- OCV concepts
- Derates
- PBA timing
- Hierarchical STA flows
- Physical design closure
- Tcl
Salary Information not included
Sr. Staff Analog Design Engineer
- Synopsys
- Office Location
- Full Time
- Analog Design
- Electronics Engineering
- scripting languages
- Perl
- Python
- Automation
- IP characterization
- CAD view generation
- Design simulation environments
- EDA views
- IO designs
- Digital implementation flows
Salary Information not included
Accounts Payable / Receivable, Manager
- Synopsys
- Office Location
- Full Time
- Accounts Payable
- Accounts Receivable
- finance
- financial management
- Accounting
- Managerial Skills
Salary Information not included
Software Engineer
- Synopsys
- Office Location
- Full Time
- C
- algorithms
- EDA
- static timing analysis
- datastructures
- Intel TBB
Salary Information not included
Analog Design, Staff Engineer
- Synopsys
- Office Location
- Full Time
- Analog Design
- ESD
- signal integrity
- Power Integrity
- Highspeed IO designs
- reliability concepts
- JEDEC requirements
Salary Information not included
Senior Staff ASIC Digital Design
- Synopsys
- Office Location
- Full Time
- Verilog
- SystemVerilog
- Bash
- Python
- Perl
- CC
- Tcl
Salary Information not included
R&D Engineering, Principal
- Synopsys
- Office Location
- Full Time
- Computer Science
- Problem Solving
- Technology
- Software Engineer
- Collaborative
- Team player
INR 2 Lacs - INR 3 Lacs /year
ASIC Digital Design, Architect
- Synopsys
- Office Location
- Full Time
- UFS
- AMBA
- Ethernet
- DDR
- PCIe
- USB
- Verilog
- Perl
- Python
- architecting verification environments
- HVL System Verilog
- functional coverage
- VMMOVMUVM
- MIPII3C
- Unipro
- SDeMMC
- Tcl
- VIP development
Salary Information not included
Finance Manager
- Synopsys
- Office Location
- Full Time
- MIS
- Analytics
- SAP BPC
- SAP BW
- Excel
- Power Bi
- Tableau
- Python
- Financial Planning Analysis
Salary Information not included
Mac OS Virtualization Specialist
- Synopsys
- Office Location
- Full Time
- Apple hardware
- Apple software
- vmware
- Parallels
- Networking
- Jamf Pro
- Mac OS parallel virtualization technologies
- Storage protocols
Salary Information not included
Silicon Validation Engineer
- Synopsys
- Office Location
- Full Time
- FPGA Design
- HDL
- SystemVerilog
- VB SCRIPT
- Python
- Bash
- Statistical Analysis
- Data Analysis
- PCB schematic capture
- Cad Software
- Tcl
Salary Information not included
Sr. Staff Verification Expert
- Synopsys
- Office Location
- Full Time
- UVM
- System Verilog
- Python
- Perforce
- PCIe
- AMBA
- AXI
- APB
- AHB
- IP Design Verification
- Tcl
- CXL
- UCIe