Apply For ASIC Desing Verification Lead - Bangalore

• UST
• Office Location
• Full Time

Experience: 8 - 8 years required

Pay:

Salary Information not included

Type: Full Time

Location: All India

Skills: Verilog, System Verilog, UVM, IP Verification, RTL, Power Aware Verification, Gate level verification, AXI4, AXI5 protocol, Coherency rules, BFMs, VIPs, Chip level verification infrastructure