ASIC Desing Verification Lead - Bangalore UST
UST
Office Location
Full Time
Experience: 8 - 8 years required
Pay:
Salary Information not included
Type: Full Time
Location: All India
Skills: Verilog, System Verilog, UVM, IP Verification, RTL, Power Aware Verification, Gate level verification, AXI4, AXI5 protocol, Coherency rules, BFMs, VIPs, Chip level verification infrastructure
About UST
Job Description
Hi All, Experience 8 to 15years Job Description Good understanding of verification concepts and techniques. Very good knowledge of Verilog/System Verilog and UVM. Experience and knowledge in Verification of IPs related to different applications. Good Knowledge in Power aware verification and Gate level verification is preferable. Should be able to understand the Full-chip Verification requirements as well and good knowledge in industry standard protocols. Verification for complex IPs and close the Verification to the challenging milestones. Strong knowledge of AXI4/AXI5 protocol Strong understanding of Coherency rules in ACE and ACE5 Experience with architecting BFMs/VIPs Should be able to handle a team of 3-4 engineers. IP Verification: VR creation as per the chip requirements and UVM/OVM Test benches creation Support in building verification infrastructure at the chip level as per the requirements. Capable of handling multiple areas of IP Verification: RTL, Power Aware and Gate Level Verification Please forward your resume to jayalakshmi.r2@ust.com Regards, Jaya,