ASIC Digital Design, Architect Synopsys
Synopsys
Office Location
Full Time
Experience: 15 - 15 years required
Pay:
Salary Information not included
Type: Full Time
Location: Noida
Skills: UFS, AMBA, Ethernet, DDR, PCIe, USB, Verilog, Perl, Python, architecting verification environments, HVL System Verilog, functional coverage, VMMOVMUVM, MIPII3C, Unipro, SDeMMC, Tcl, VIP development
About Synopsys
Job Description
The candidate will be part of the DesignWare IP Verification R&D team at Synopsys. You will be expected to specify, design/architect, and implement state-of-the-art Verification environments for the DesignWare family of synthesizable cores and perform Verification tasks for the IP cores. You will work closely with RTL designers and be part of a global team of professional Verification Engineers. You will be working on the next generation connectivity protocols for Commercial, Enterprise, and Automotive applications. Your job role will have a combination of Test planning, Test environment coding both at unit level and system level, Test case coding, debugging, FC coding and testing, meeting quality metric goals, and regression management. Requirements: - Must have BSEE in EE with 20+ years of relevant experience or MSEE with 15+ years of relevant experience. - Prior experience in architecting verification environments for complex serial protocols is a must. - Experience in developing HVL (System Verilog) based test environments, developing and implementing test plans, implementing and extracting verification metrics such as functional coverage is required. - Exceptional HVL coding skills for Verification and hands-on experience with one or more Industry standard simulators such as VCS, NC, MTI used in Verification and waveform-based debugging tools. - Proficient in verification methodologies such as VMM/OVM/UVM is required. - Exposure to Formal verification methodologies is highly desirable. - Knowledge of one or more of protocols: MIPI-I3C/UFS/Unipro, AMBA (AMBA2, AXI), SD/eMMC, Ethernet, DDR, PCIe, USB. - Familiarity with HDLs such as Verilog and scripting languages such as Perl, TCL, Python is highly desired. - Exposure to IP design and verification processes including VIP development is highly desirable. - Exceptional focus on functional coverage-guided methodology is essential. So, the corresponding mindset is a must. - Good written and oral communication skills are required, along with the ability to demonstrate good testing, debug, and problem-solving skills and show high levels of initiative.,