Staff RTL Design Mulya Technologies

About Mulya Technologies

Job Description

As an RTL design lead located in Bangalore, you will be a crucial part of designing and developing complex ASICs and System-on-Chip architectures for various electronic devices. Your duties will involve RTL design, implementing effective design practices, converting micro-architecture into efficient RTL, optimizing performance, power efficiency, and area constraints, all while ensuring alignment with system-level requirements. Additionally, you will be tasked with defining and validating analog-digital interfaces. Your responsibilities will include collaborating with architecture and physical design teams to code power/area/performance optimized RTL, participating in verification at block and chip levels, conducting Lint, CDC/RDC, LEC checks, developing block and chip level constraints, and performing synthesis. To qualify for this role, you should possess a Bachelor's, Master's, or Ph.D. degree in Electrical Engineering along with 7-10 years of industry experience. Proficiency in hardware description languages such as Verilog, VHDL, and microarchitecture modeling tools like SystemVerilog and SystemC is essential. Experience with SoC design methodologies, including RTL design, synthesis, and timing analysis, is required. It is important to have the ability to self-verify RTL blocks/top level before handing off to the DV team. Exposure to Analog digital interfaces and physical layer development for standards like Ethernet, USB3, MIPI is highly desirable. Familiarity with STA, DFT, and physical design is also preferred. Excellent communication and teamwork skills are necessary, as well as being a self-starter and a highly motivated individual contributor. If you meet the qualifications and are interested in this opportunity, please contact Uday at Mulya Technologies via email at muday_bhaskar@yahoo.com.,