Principal IP RTL Design Engineer DDR / LPDDR Mulya Technologies
Mulya Technologies
Office Location
Full Time
Experience: 7 - 7 years required
Pay:
Salary Information not included
Type: Full Time
Location: All India
Skills: RTL design, DDR, LPDDR, HBM controller architecture
About Mulya Technologies
Job Description
Principal / Staff IP RTL Design Engineer DDR/LPDDR Bangalore Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/Bangalore A US based well-funded product-based startup looking for Highly talented RTL Design Engineers for the following roles. IP RTL Design Engineer DDR/LPDDR We're a US-based startup building cutting-edge solutions for the High Performance Computing (HPC) market and we're growing! If you have experience in DDR, LPDDR, or HBM IP development and are looking for your next challenge, we want to hear from you. Role: IP RTL Design Engineer Level: Mid-Senior to Senior Location: Bengaluru (hybrid) What You'll Bring: 7-12 years of experience Solid RTL design and micro-architecture experience Deep knowledge in DDR/LPDDR or HBM controller architecture Experience building high-performance, low-latency memory subsystems Passion for working in fast-paced, innovation-driven environments Why Join Us Shape the future of memory IP for HPC applications Be part of a nimble, expert-driven team solving hard technical problems Competitive compensation and real ownership in a rapidly growing startup Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community",