AMS Verification Engineer Mulya Technologies
Mulya Technologies
Office Location
Full Time
Experience: 2 - 2 years required
Pay:
Salary Information not included
Type: Full Time
Location: All India
Skills: Scripting, UVM, System Verilog, Specman, GLS, CPF, UPF, AMS, C based SOC DV, Firmware verification, PAGLS, Cadence tools, CDC DV, FW DV, Formal, Post silicon verification
About Mulya Technologies
Job Description
AMS Verification Engineer Top10 Semiconductor Organization in the World Bangalore Job Responsibilities : Complete ownership of IP / subsystem / SOC chip DV. This includes : Responsible for driving verification strategy, creating Test Plans and developing Test Benches for IPs and SoC. Active involvement with architecture team during the spec definition phase Verification strategy definition along with Verification plan to meet 100% spec to regression traceability along with signoff metrics IP / SS / SOC verification covering functional and Firmware scenarios in RTL, GLS modes. DV Environment ownership : TB development / enhancements including checkers and coverage monitor definitions along with DV flow updates as per the project needs Active collaboration with cross functional teams -Architecture, RTL, PD, DFT, Systems, Analog, FW and application teams -to enable the Verification goals for IP / Subsystem / SOC starting from spec definition till post silicon verification closure activities Final SoC DV signoff based on Regressions, coverage metrics, DV to spec traceability Minimum requirements : 2-5 years of DV experience in IP / SOC DV with a Bachelor or Masters degree in EE / ECE / CS or related specializations Preferred Skills : Excellent debugging and problem-solving skill Effective communication skills to interact with all stakeholders Team and People Skills : The candidate should have good people skills to work closely with the architecture and product apps team. Experience in one or many of the following : C based SOC DV, Firmware verification exposure, scripting (Perl / Python / ML based DV) knowledge DV flow ownership for functional / Firmware verification, UVM / System Verilog deep understanding, Specman, GLS / PAGLS / CPF / UPF based verification, Post silicon verification etc. Experience with Cadence tools (Xcelium / vManager / Formal JG applications / safety simulator) or similar tools / DV flows Exposure to AMS, CDC DV, FW DV, Formal, Post silicon verification Must be highly focused and remain committed to obtaining closure on project goals Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community",