Apply For WLAN PHY Baseband(RTL) Digital Design Engineer -Sr Eng

• Qualcomm
• Office Location
• Full Time

Experience: 1 - 1 years required

Pay:

Salary Information not included

Type: Full Time

Location: Karnataka

Skills: System Verilog, Visio, Verilog RTL coding, uArch, CDC check, PLDRC, Timing Constraints, PythonPerl, Knowledge of signal processing conceptsalgorithms, WiFi standards 80211abgnacax, HLS