Apply For Title Senior RTL Design Engineer

• Pixxel
• Office Location
• Full Time

Experience: 4 - 4 years required

Pay:

Salary Information not included

Type: Full Time

Location: All India

Skills: Verilog, System Verilog, VHDL, SPI, I2C, LVDS, C, Python, Matlab, Xilinx Vivado Design Suite