Apply For Technical Lead II - VLSI (Analog Circuit Design)
UST Global
Office Location
Full Time
Experience: 7 - 7 years required
Pay:
Salary Information not included
Type: Full Time
Location: Karnataka
Skills: System Verilog, Verilog, VHDL, UVM, C, Assembly, Perl, TCLTK, Makefile, SPICE, Lint, Calibre, Micro architecture, physical design, circuit design, Analog Layout, synthesis, DFT, Floorplan, Clocks, PR, Physical verification, FPGA Design, Communication skills, analytical reasoning, EDA, RTL design, STA, PV, LDO, OTA, Cadence, SYNOPSYS, Mentor, CDCRDC, DCRTLC, ICCInnovusOlympus, ETSTKFS, PTTempus, IP Spec Architecture Design, Functional Spec Test Plan Verification, Bus Protocol AHBAXIPCIeUSBEthernetSPII2C, Financial Modeling
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