Apply For Technical Lead I - VLSI Mem D&C

• UST Global
• Office Location
• Full Time

Experience: 8 - 8 years required

Pay:

Salary Information not included

Type: Full Time

Location: Noida

Skills: System Verilog, Verilog, VHDL, UVM, C, Assembly, Perl, TCLTK, Makefile, SPICE, Lint, Calibre, Micro architecture, physical design, circuit design, Analog Layout, synthesis, DFT, Floorplan, Clocks, PR, Physical verification, FPGA Design, Strong Communication Skills, Cadence, SYNOPSYS, Mentor, CDCRDC, DCRTLC, ICCInnovusOlympus, ETSTKFS, PTTempus, IP Spec Architecture Design, Functional Spec Test Plan Verification, Bus Protocol AHBAXIPCIeUSBEthernetSPII2C, Microprocessor architecture, STA Extraction, Soft Hard Mixed Signal IP Design, Processor Hardening, CMOS FinFet FDSOI 28nm 22nm 16ff 10nm, below, Microsoft Excel