Apply For Synthesis & STA Engineers

• Adroitec Systems
• Office Location
• Full Time

Experience: 3 - 3 years required

Pay:

Salary Information not included

Type: Full Time

Location: Karnataka

Skills: STA, DFT, Mbist, SCAN, static timing analysis, Power analysis, Verilog, System Verilog, Perl, PTPX, UPF, RTL Synthesis, Timing Constraints, Power intent, LowPower checks, Logic Equivalency Checks, ECO Flows, Tcl, Makefile scripting, Power Artist, Gate Level simulations, SDF, Functional ECO implementation