Apply For Staff RTL/ FPGA Design Engineer

• Synopsys Inc
• Office Location
• Full Time

Experience: 8 - 8 years required

Pay:

Salary Information not included

Type: Full Time

Location: Hyderabad

Skills: Design, Validation, PCIe, USB, protocols, Testing, Programming Languages, SystemVerilog, Verilog, Perl, Python, emulation, Communication, collaboration, FPGAbased solutions, CXL, Hardware Assisted Verification, highspeed protocols, Tcl, Prototyping Platforms, ZeBu, HAPS, Problemsolving