Apply For Staff Engineer ASIC Digital Design (DDR PHY)

• Micron
• Office Location
• Full Time

Experience: 7 - 7 years required

Pay:

Salary Information not included

Type: Full Time

Location: Hyderabad

Skills: Verilog, scripting languages, Microarchitecture, synthesis, STA, Asynchronous digital designs, Lint CDC, DDRLPDDR JEDEC protocol, DDR PHY designs, DDR training algorithms, data path designs, domain transfer designs, APBJTAG, DFI