Apply For SOC Power Design -Sr Eng/Sr Lead/Staff/Sr Staff

• Qualcomm
• Office Location
• Full Time

Experience: 2 - 2 years required

Pay:

Salary Information not included

Type: Full Time

Location: Hyderabad

Skills: CPF, Low power intent concepts, languages UPF, Power Estimation, reduction tools PowerArtistPTPX, Calypto, Power dissipation, power savings techniques Dynamic clock, voltage scaling, Power analysis Leakage, Dynamic, Thermal Impacts, Power Software features for power optimization, Voltage regulators including Buck, Low Drop out, ASIC Power grids, PCB Power Distribution Networks, Mobile Baseband application processors chipset, power grid understanding, UPFbased synthesis, implementation using Design Compiler, Structural low power verification tools like CLP, MVRC, Outsta