Apply For SoC Debug DV Sr Lead / Staff Engineer

• Qualcomm
• Office Location
• Full Time

Experience: 7 - 7 years required

Pay:

Salary Information not included

Type: Full Time

Location: Karnataka

Skills: Verilog, System Verilog, UVM, Soc level verification testbench, debug architecture, Power aware simulations, Gate Level simulations, AHBAXI ATBAMBA protocol