Apply For Signoff And Design Methodology Engineer, Silicon

• Google
• Office Location
• Full Time

Experience: 5 - 5 years required

Pay:

Salary Information not included

Type: Full Time

Location: Karnataka

Skills: static timing analysis, synthesis, physical design, Automation, Verilog, SystemVerilog, Electromigration, Physical Design Tool Automation, Extraction of Design Parameters, Quality of Results Metrics, Analyzing Data Trends, Timing Constraints, Convergence, Signoff, Parasitic Extraction Tools, RegisterTransfer Level RTL Languages, Static Timing Analysis STA, IR Drop EMIR, PDV Signoff Methodologies