Apply For Senior Principal Verification Engineer

• Cadence Design Systems
• Office Location
• Full Time

Experience: 10 - 10 years required

Pay:

Salary Information not included

Type: Full Time

Location: Noida

Skills: RTL, Verilog, SystemVerilog, Scripting, Excellent Communication Skills, Ability to ramp up on new technologies quickly, independently, Scalable designs, Emulation Platform