Apply For Senior Principal Digital Design Engineer

• onsemi
• Office Location
• Full Time

Experience: 10 - 10 years required

Pay:

Salary Information not included

Type: Full Time

Location: Karnataka

Skills: synthesis, timing analysis, physical design, Microarchitecture, RTL design, CDC, ASIC Synthesis, PR, UPF, System Verilog, Verilog, Perl, Python, XML programming, RTL implementation, Power convertor controller design, Digital design architecture, Low power design, RTL2GDS flows, ASICMixed signal chip developments, Tcl