Apply For Senior Memory Design Lead Engineer

• ACL Digital
• Office Location
• Full Time

Experience: 8 - 8 years required

Pay:

Salary Information not included

Type: Full Time

Location: All India

Skills: Understanding of computer architecture, concepts, Basic understanding of CMOS Transistors, their behaviors, Understanding of high speedlow power CMOS circuit design, clocking scheme, Static, complex logic circuits, Understanding of Power versus Performance versus Area tradeoffs in typical CMOS design, Engineering demeanor, Passion for Circuit design, Good interpersonal skills, Basic scripting languages eg PerlTCLPython, Experience of working on Cadence, Synopsys flows, Experience with Circuit Simulation, Optimization of standard cells