Apply For RTL Verification Engineer - System Verilog

• Semi Leaf
• Office Location
• Full Time

Experience: 5 - 5 years required

Pay:

Salary Information not included

Type: Full Time

Location: Hyderabad

Skills: RTL verification, System Verilog, UVM, Debugging, scripting languages, SoC architecture, standard protocols, Xilinx FPGA verification, Version Control Systems, AgileScrum environments, cloudbased verification environments, coveragedriven verification