Apply For RTL Design Lead /Manager

• BITSILICA
• Office Location
• Full Time

Experience: 8 - 8 years required

Pay:

Salary Information not included

Type: Full Time

Location: Hyderabad

Skills: RTL design, Verilog, SystemVerilog, Debugging, scripting languages, Spyglass, Verdi, VCS, ASIC design flow, AMBA protocols, Problemsolving, highspeed protocols, Synopsys DC