Apply For RTL DESIGN LEAD ENGINEER

• SmartSoC Solutions
• Office Location
• Full Time

Experience: 8 - 8 years required

Pay:

Salary Information not included

Type: Full Time

Location: Karnataka

Skills: AHB, System Verilog, front end ASIC tool flows, ARM based SoC Architecture, ARM Cortex AM integration, SoC DV methodology, LowPower design methodology, ASIC tools Lint, Verilog RTL coding, Power aware RTL codingdesign, ClockStructuresScheme, Good Communication Skills