Apply For RTL Design Engineer, Core-IP, Silicon

• Google
• Office Location
• Full Time

Experience: 4 - 4 years required

Pay:

Salary Information not included

Type: Full Time

Location: Karnataka

Skills: Verilog, SystemVerilog, synthesis, DFT, SoC architecture, digital logic design principles, RTL design concepts, ASIC, FPGA design verification, timingpower analysis, highperformance design techniques, lowpower design techniques, assertionbased formal verification, FPGA platforms, Emulation platforms