Apply For Principal Product Validation Engineer

• Cadence Design Systems
• Office Location
• Full Time

Experience: 5 - 5 years required

Pay:

Salary Information not included

Type: Full Time

Location: Noida

Skills: Verilog, VHDL, EDA tools, SystemVerilog, C, UVM, Functional verification, SoC verification, PCIe, DP, HDLs, Hardware Verification Language, USB34