Apply For Physical Design Engineer

• Lattice Semiconductor
• Office Location
• Full Time

Experience: 12 - 12 years required

Pay:

Salary Information not included

Type: Full Time

Location: Maharashtra

Skills: RTL, CTS, Routing, floorplanning, timing, Physical verification, DRC, LVS, Perl, Python, FPGA Design, Calibre, GDSII, place route, powerplanning, physical signoff, physical design signoff checks, EMRV, Scripting Knowledge, ASIC blocks, Innovus, Genus, Tempus, voltus, conformal, Problemsolving, multisite collaboration