Apply For Multimedia Core IP RTL Design Engineer, Silicon

• Google
• Office Location
• Full Time

Experience: 4 - 4 years required

Pay:

Salary Information not included

Type: Full Time

Location: Karnataka

Skills: RTL Coding, video codecs, Verilog, SystemVerilog, Lint, CDC, UPF, ASIC design methodologies, Camera ISP image processing blocks, Video processing blocks, Machine Learning IPs, multimedia IPs, Display, clock domain checks, reset checks, FV