Apply For Mixed Signal Verification

• Texas Instruments
• Office Location
• Full Time

Experience: 1 - 1 years required

Pay:

Salary Information not included

Type: Full Time

Location: Karnataka

Skills: Verilog, Power management, Cadence Virtuoso, Spectre, RTL, AMS Design Verification, VerilogA, VerilogAMS, Signal Management, Full chip DV, Analog power IPs, SPICE simulation, Incisive, AMS simulators, Gates, SDF, Process variation, Backannotated timing simulations, Parasitic resistance, Parasitic capacitance, Assura parasitic extraction tools, Constrainedrandom stimulus, Autochecking verification environments, Design for Verification architecture