Apply For Memory Design Validation Engineer

• UST
• Office Location
• Full Time

Experience: 5 - 5 years required

Pay:

Salary Information not included

Type: Full Time

Location: Karnataka

Skills: reliability analysis, Communication skills, Interpersonal Skills, leadership skills, development of memory macros, transistor level circuit behavior, Analysis, layout challenges in sub nanometer process technologies, signal integrity analysis, EMIR analysis, memory behavioral, physical models, DFT Schemes, chip level integration, transistor level simulators, automation scripts, Cadence schematiclayout editor tools, Monte Carlo variation analysis, waveform viewer tools, SkillPerlPython Scripting, Debugging skills, Problem solving skills, Logical reasoning skills, Multitasking Skills