Apply For Lead Physical Design Engineer

• Cyient
• Office Location
• Full Time

Experience: 5 - 5 years required

Pay:

Salary Information not included

Type: Full Time

Location: Hyderabad

Skills: floorplanning, Placement, CTS, Routing, STA, Physical verification, Perl, static timing analysis, PTPX, Redhawk, Netlist2GDSII Implementation, Power Grid Design, Power Integrity Analysis, Chip finishing, Analog, Mixed Signal Design, Tcl, Tk, PNR Suite from Cadence Synopsys, Innovus, ICC2, PrimeTime SI, EMIRDrop analysis, Complex SOC integration, Low power design, HighSpeed Design, Advanced Physical Verification Techniques